Integrated circuit memory devices containing multiple banks of memory arrays frequently utilize shared data routing circuitry to support efficient write and read operations. An example of a data routing circuit that is shared by multiple memory arrays is illustrated by FIG. 1. In particular, FIG. 1 illustrates an input/output data routing circuit 20 that is electrically coupled to a pair of memory cell arrays 10a and 10b, which are shown as including dynamic random access (DRAM) memory cells (MC). The illustrated memory cells MC in the pair of memory cell arrays 10a and 10b are electrically coupled to the input/output data routing circuit 20 by respective pairs of differential bit lines BL and /BL.
The input/output data routing circuit 20 includes left and right equalization and isolation circuits 12a and 12b that are electrically coupled by corresponding pairs of differential bit lines BL and /BL to respective columns of memory cells within the memory cell arrays 10a and 10b. The left equalization and isolation circuit 12a is illustrated as including three NMOS equalization transistors that are responsive to an active high first equalization signal PEQi. Switching this first equalization signal PEQi from low-to-high operates to pull the corresponding bit lines to an equivalent voltage Vequal having a magnitude about equal to a voltage of the VBL reference line (e.g., Vequal=VBL−Vth, where Vth is a threshold voltage of an NMOS transistor). The left equalization and isolation circuit 12a also includes a pair of NMOS pass transistors that are responsive to a first isolation signal PISOi. When the first isolation signal PISOi is switched low-to-high, the pair of differential bit lines BL and /BL from the left memory cell array 10a are electrically connected to a pair of differential sense bit lines SBL and /SBL. Similarly, the right equalization and isolation circuit 12b is illustrated as including three NMOS equalization transistors that are responsive to an active high second equalization signal PEQj. Switching of this second equalization signal PEQj from low-to-high operates to pull the corresponding bit lines to the equivalent voltage Vequal. The right equalization and isolation circuit 12b also includes a pair of NMOS pass transistors that are responsive to a second isolation signal PISOj. When the second isolation signal is switched low-to-high, the pair of differential bit lines BL and /BL from the right memory cell array 10b are electrically connected to the pair of differential sense bit lines SBL and /SBL. As will be understood by those skilled in the art, in order to provide adequate isolation between the memory arrays, the first and second isolation signals are not active during overlapping time intervals.
A P-type sense amplifier block 14 and an N-type sense amplifier block 18 collectively form a sense amplifier that is responsive to a pair of complementary control signals LA and LAB. When the control signal LA is switched low-to-high and the control signal LAB is switched high-to-low, the P-type sense amplifier block 14 and the N-type sense amplifier block 18 become active and operate to sense and amplify any differential signal established across the pair of sense bit lines SBL and /SBL. A column select IO block 16 is also provided in a column gate region (CGR). This column select IO block 16 includes a pair of NMOS transistors that are responsive to a column select signal (shown as CSL0). When the illustrated column select signal CSL0 is switched low-to-high, a rail-to-rail signal established across the sense bit lines SBL and /SBL is transferred to a pair of input/output lines IO and IOB during a read operation (or vice versa during a write operation). These input/output lines IO and IOB are illustrated as extending orthogonal to the bit lines BL and BLB. These and other aspects of the input/output data routing circuit of FIG. 1 are more fully described in commonly assigned U.S. Pat. Nos. 5,701,268, 6,046,950 and 6,396,756. Multi-bank memory devices with input/output routing circuitry are also disclosed in commonly assigned U.S. Pat. Nos. 5,485,426, 5,949,697, 6,067,270 and 6,327,214.
The layout of the input/output data routing circuit 20 of FIG. 1 may result in many closely spaced pairs of input/output lines IO and IOB when multiple data routing circuits 20 are positioned side-by-side in the direction of the input/output lines IO and IOB. An example of a memory device that utilizes closely spaced input/output lines IO and IOB is illustrated by FIG. 2, which is a reproduction of FIG. 3 of U.S. Pat. No. 6,345,011 to Joo et al. In FIG. 2, a multi-bank memory device is illustrated as including memory banks MB0, MB1 and MB2. A first sense amplifier block SABLK0 extends between memory banks MB0 and MB1 and a second sense amplifier block SABLK1 extends between memory banks MB1 and MB2. These memory banks are illustrated has having 2052 pairs of bit lines (BL0, /BL0 to BL2051, /BL2051), with the even pairs of bit lines extending to one sense amplifier block and the odd pairs of bit lines extending to another sense amplifier block. Each of the sense amplifier blocks SABLK0 and SABLK1 includes a left side bit isolation circuit 50, a right side bit isolation circuit 60 and a bit line precharging and equalization circuit 70 of conventional design (see, e.g., FIG. 1). A P-type sense amplifier circuit 80 and an N-type sense amplifier circuit 90 are also provided on opposite sides of a column select IO circuit 100, which is responsive to column select signals (e.g., CSL0–CSL512). The column select IO circuit 100 is illustrated as including a plurality of column select IO blocks that are arranged side-by-side in a single row, with each block including a pair of column selection transistors (GT). Each pair of column selection transistors GT routes data from a corresponding pair of sense bit lines to a respective pair of closely spaced input/output (IO) lines, shown as (IOi, /IOi), (IOj, /IOj), (IOk,/IOk) and (IOl, /IOl), and vice versa, when a respective column select signal is active.
Unfortunately, such close spacing of the IO lines can result in reliability failures when a sufficient layout pitch is not maintained between the adjacent lines. To address this possibility of reliability failures, the layout area of the column select IO circuit 100 can be increased, but such area increases result in lower integration densities and/or lower memory bandwidth, which is a function of memory speed and data path bandwidth.
One attempt to address the reliability and/or data path bandwidth limitations associated with the memory device of FIG. 2 utilizes the column select IO circuit of FIG. 3, which is a reproduction of FIG. 5 of the Joo et al. patent. As illustrated by FIG. 3, an interface region 200 is provided between upper array (UA) portions of the memory blocks and lower array (LA) portions of the memory blocks. This interface region 200 provides sufficient area to reroute input/output lines IOi, IOj, /IOi and /IOj associated with the upper array (UA) away from the input/output lines IOk, IOl, /IOk and /IOl associated with the lower array (LA), and thereby maintain sufficient pitch between adjacent IO lines. However, as illustrated by FIGS. 6B and 6C of the Joo et al. patent, the rerouting of input/output lines may require the use of additional levels of metallization and contact vias and thereby complicate the process for fabricating the memory device. Moreover, the rerouting of the input/output lines may require a greater layout area to accommodate the interface region 200.